1. Field of the Invention
The present invention relates to the field of MEMS (microelectro-mechanical systems) and wafer level packaging.
2. Prior Art
Prior art MEMS devices are typically fabricated using conventional processing techniques generally found in integrated circuit fabrication. They differ from integrated circuits, however, in that MEMS devices generally have moveable members requiring partially unsupported structures, such as cantilevered members, diaphragms and the like.
Silicon is generally used in MEMS technology and etched to create cavities. Either deep reactive ion etching or wet etch in KOH or TMAH solutions are used. Deep reactive ion etching leads to vertical edge of the cavity and wet etch leads to slopes in a similar way AlN can be etched. This is well documented in the literature. The major limitation here is that only monocrystalline Si can be used, hence a bulk substrate. There are no possibilities to have structures like inductors embedded below. The cavity in the silicon substrate has various disadvantages, including the fact that dimensions are not readily controllable and that being in the substrate itself, MEMS devices cannot be fabricated over an integrated circuit, thereby requiring a larger chip area for incorporating both MEMS devices and associated integrated circuitry.
Polymer materials can be deposited, but there are limitations to the use of such material in MEMS devices. SU8 resist is popular in MEMS technology, allowing for high aspect ratios and vertical walls as high as 80 microns. But polymers are generally low temperature materials only, show poor adhesion, cannot be etched properly with curves, may degas and are not hermetic.
Wafer level packaging has advantages in efficiency and avoids the handling of individual devices until the final dicing of the completed devices. However ease of wafer level packaging and reliability of the resulting packages are of paramount importance.